1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having improved replacement efficiency of defective word lines by redundancy word lines in a semiconductor memory device having a plurality of banks.
2. Description of the Related Art
In semiconductor memory devices, in particular, in Dynamic Random Access Memories (DRAMs), the concept of a bank is introduced to increase the efficiency of data access time, which is known as an access time tAC. A bank is one or a plurality of DRAM blocks sharing timing control signals. Memories in a bank share a data bus, an address, and a control signal line. However, each bank is an independent chip that has a row decoder and a column decoder. An inherent DRAM operation can be performed in each bank.
Because banks are independent, while data are read in one bank, a pre-charge or refresh operation is performed, or a word line selection operation using a new row address can be performed in another bank. Accordingly, if an operation of selecting word lines is performed in another bank while data are read from a sense amplifier of one bank, a row access time of a DRAM can be reduced greatly. Therefore, a time loss can be reduced by increasing the number of banks.
However, if the number of banks is increased in a redundancy circuit, which is used to replace a defective memory cell with an operational memory cell, redundancy efficiency is reduced as a result of the increase in the number of banks.
FIG. 1 shows a conventional semiconductor memory device 1000 having a plurality of banks. As shown in FIG. 1, the semiconductor memory device 1000 includes a plurality of banks 100, 101, 102, 103, and 104, a plurality of sense amplifiers 110, 111, 112, and 113 placed between one bank and another bank, a plurality of switching circuits 120, 121, 122, 123, 124, 125, 126, and 127 placed between a bank and a sense amplifier, and control circuits 131, 132, and 133.
Referring to FIG. 1, if a second bank 102 is activated, sense amplifiers 111 and 112 that are adjacent to the second bank 102 operate. Therefore, a first bank 101 and a third bank 103 can be activated. Accordingly, the first bank 101 and the third bank 103 cannot use the respective sense amplifiers 111 and 112. A bank 100 and a fourth bank 104 are not adjacent to the activated second bank 102, and thus can be activated together with the second bank 102.
Accordingly, if a word line fault occurs in the second bank 102, the defective word line cannot be replaced by redundancy word lines of the first bank 101 and the third bank 103 adjacent to the second bank 102.
Assuming one block is used as one bank, if a defective word line occurs in the bank, the defective word line should be replaced only by redundancy word lines of the bank. Thus, the bank must include a significant number of redundancy word lines so as to obtain an adequate yield. The significant number of redundancy word lines necessarily increases the size of a semiconductor memory chip.
An exemplary embodiment of the present invention provides a semiconductor memory device have redundancy efficiency, in which a defective word line may be restored using redundancy word lines of two adjacent banks.
One exemplary embodiment of the present invention provides a semiconductor memory device having a plurality of banks, where each bank includes a plurality of normal word lines and a plurality of redundancy word lines. The redundancy word lines are used to replace a defective word line if required.
The exemplary embodiment further includes a plurality of sense amplifiers, where each of the plurality of sense amplifiers is placed between one adjacent bank and another adjacent bank. The sense amplifiers sense and amplify data on a bit line of a respective bank. In addition, a plurality of switching circuits are provided, where each switching circuit is placed between a bank and a sense amplifier. The switching circuits are capable of transmitting data on a bit line of a bank to a sense amplifier in response to a control signal, which is generated by a control signal generator.
When defects occur in the normal word lines of the bank, they are replaced by redundancy word lines of two banks adjacent to the bank. The control signal is used to disable the switching circuits connected to the bank containing the defective word lines. Moreover, the control signal is used to enable each of the switching circuits placed between the bank and each of the adjacent banks, and between the bank and each of the adjacent sense amplifiers. The defective word lines of the bank are replaced by the redundancy word lines of the two banks adjacent to the bank by enabling the redundancy word lines of the two banks adjacent to the bank.
In an exemplary embodiment, when the defected word line of the bank is replaced by the redundancy word lines of the bank, the control signal is used to enable the switching circuits connected to the enabled bank and disable the switching circuits connected to the banks adjacent to the bank.
According to an exemplary embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device includes a plurality of banks, each having normal word lines and redundancy word lines, and a plurality of sense amplifiers, each of which is placed between one adjacent bank and another adjacent bank. The sense amplifiers sense and amplify data on a bit line of each bank.
When a word line becomes defective as a result of a defect in the normal word lines of a bank, it is replaced by redundancy word lines of those banks adjacent to the bank having the defective word line. The redundancy word lines, as required, of each of the banks adjacent to the bank are simultaneously enabled, and each of the sense amplifiers placed between the bank and each of the banks adjacent to the bank senses and amplifies data of redundancy word lines of each of the banks adjacent to the bank.
Furthermore, according to an embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device includes a plurality of banks, each having normal word lines and redundancy word lines. The device further includes a plurality of sense amplifiers, each of which is placed between one adjacent bank and another adjacent bank, which senses and amplifies data on a bit line of each bank, and a plurality of switching circuits, each of which is placed between each bank and each sense amplifier, which transmits the data on the bit line of the bank to the sense amplifier in response to a control signal. Moreover, a control signal generator is provided that generates the control signal.
When a word line becomes defective as a result of a defect in the normal word lines of a bank, it is replaced by redundancy word lines of each of the banks adjacent to the bank. The redundancy word lines of each of the banks adjacent to the bank are simultaneously enabled, and a corresponding switching circuit transmits data of the redundancy word lines of each of the banks adjacent to the bank to a corresponding sense amplifier in response to a corresponding control signal.
Moreover, according to an embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device includes a first bank having normal word lines and redundancy word lines and second and third banks adjacent to the first bank in both directions, first and second sense amplifiers, each of which is placed between the first bank and the second bank and between the first bank and the third bank, connected to bit lines of each of the first through third banks, senses and amplifies data. Furthermore, first, second, third, and fourth switching circuits are provided, each of which is connected between the second bank and the first sense amplifier, between the first sense amplifier and the first bank, between the first bank and the second sense amplifier, and between the second sense amplifier and the third bank. The switching circuits are for connecting each of the banks to each of the sense amplifiers in response to a control signal, which is generated by a control signal generator and is used to control the first through fourth switching circuits.
When a word line becomes defective as a result of a defect in the normal word lines of a bank, it is replaced by redundancy word lines of the second and third banks. The control signal is used to disable the second and third switching circuits and is used to enable the first switching circuit and the fourth switching circuit, and the defected word line of the first bank is replaced by the redundancy word lines of the second and third banks by simultaneously enabling the redundancy word lines of the second and third banks.
In an exemplary embodiment of the present invention, when the defected word line of the first bank is replaced by the redundancy word lines of the first bank, the control signal is used to enable the second and third switching circuits and disable the first and fourth switching circuits.
In an exemplary embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device includes first, second, and third banks, each having normal word lines and redundancy word lines, a first sense amplifier which is placed between the first bank and the second bank, which senses and amplifies data on bit lines of the first and second banks in response to a first corresponding control signal. Moreover, the semiconductor device includes a second sense amplifier which placed between the first bank and the third bank, which senses and amplifies data on bit lines of the first and third banks in response to a second corresponding control signal.
When a word line becomes defective as a result of a defect in the normal word lines of a bank, it is replaced by redundancy word lines of the second and third banks, the redundancy word lines of the second bank and the redundancy word lines of the third bank are activated, the first sense amplifier senses and amplifies data of the redundancy word lines of the second bank in response to the first control signal, and the second sense amplifier senses and amplifies data of the redundancy word lines of the third bank in response to the second control signal.
The semiconductor device may further include a fourth bank adjacent to the second bank, having normal word lines and redundancy word lines, a fifth bank adjacent to the third bank, having normal word lines and redundancy word lines, a third sense amplifier which is placed between the second bank and the fourth bank, senses and amplifies data on bit lines of the second and fourth banks in response to a third corresponding control signal, and a fourth sense amplifier which is placed between the third bank and the fifth bank, senses and amplifies data on bit lines of the third and fifth banks in response to a fourth corresponding control signal. The third and fourth sense amplifiers are deactivated in response to the third and fourth control signals.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.